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HUF75307T3ST
Data Sheet October 1999 File Number 4364.4
2.6A, 55V, 0.090 Ohm, N-Channel UltraFET Power MOSFET
This N-Channel power MOSFET is manufactured using the innovative UltraFETTM process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products. Formerly developmental type TA75307.
Features
* 2.6A, 55V * Ultra Low On-Resistance, rDS(ON) = 0.090 * Diode Exhibits Both High Speed and Soft Recovery * Temperature Compensating PSPICETM Model * Thermal Impedance SPICE Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Symbol
D
Ordering Information
PART NUMBER HUF75307T3ST PACKAGE SOT-223 5307
S
BRAND
G
NOTE: HUF75307T3ST is available only in tape and reel.
Packaging
SOT-223
DRAIN (FLANGE)
SOURCE DRAIN GATE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. UltraFETTM is a trademark of Intersil Corporation. PSPICE(R) is a trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HUF75307T3ST
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified 55 55 20V 2.6 Figure 5 Figures 6, 14, 15 1.1 9.09 -55 to 150 300 260 UNITS V V V A
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
W mW/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TA = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) Qgs Qgd CISS COSS CRSS RJA Pad Area = 0.171 in2 (see note 2) Pad Area = 0.068 in2 Pad Area = 0.026 in2 VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 30V, ID 2.6A, RL = 11.5 Ig(REF) = 1.0mA (Figure 13) TEST CONDITIONS ID = 250A, VGS = 0V (Figure 11) VGS = VDS, ID = 250A (Figure 10) VDS = 50V, VGS = 0V VDS = 45V, VGS = 0V, TA = 150oC VGS = 20V ID = 2.6A, VGS = 10V) (Figure 9) VDD = 30V, ID 2.6A, RL = 11.5, VGS = 10V, RGS = 25 MIN 55 2 TYP 0.070 5 30 35 25 14 8.3 0.6 1.00 4.00 250 115 30 MAX 4 1 250 100 0.090 55 90 17 10 0.8 110 128 147 UNITS V V A A nA ns ns ns ns ns ns nC nC nC nC nC pF pF pF
oC/W oC/W oC/W
Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Ambient
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge NOTE: 2. 110 oC/W measured using FR-4 board with 0.171in2 footprint for 1000s. SYMBOL VSD trr QRR TEST CONDITIONS ISD = 2.6A ISD = 2.6A, dISD/dt = 100A/s ISD = 2.6A, dISD/dt = 100A/s MIN TYP MAX 1.25 40 50 UNITS V ns nC
2
HUF75307T3ST Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 3.0 RJA = 110oC/W 2.5 2.0 1.5 1.0 0.5 0 25
0.8 0.6 0.4 0.2 0
0
50
100
150
50
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
10
THERMAL IMPEDANCE
ZJA, NORMALIZED
1
DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
RJA = 110oC/W
0.1 PDM t1 SINGLE PULSE t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-2 10-1 100 t, RECTANGULAR PULSE DURATION (s) 101 102 103
0.01
0.001
10-5
10-4
10-3
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100 TJ = MAX RATED TA = 25oC RJA = 110oC/W 100s 1ms 1 10ms
30
TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I
ID, DRAIN CURRENT (A)
10
IDM, PEAK CURRENT (A)
10
= I25
150 - TA 125 RJA = 110oC/W
0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1
0.01
VDSS(MAX) = 55V 200
10 100 VDS, DRAIN TO SOURCE VOLTAGE (V)
1 10-3
10-2
10-1 100 101 t, PULSE WIDTH (s)
102
103
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
3
HUF75307T3ST Typical Performance Curves
20 IAS, AVALANCHE CURRENT (A)
(Continued)
10
ID, DRAIN CURRENT (A)
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
25 VGS = 20V VGS = 10V VGS = 7V VGS = 6V
20
STARTING TJ = 25oC
15
10
STARTING TJ = 150oC
VGS = 5V
5
1 0.01
0 0.1 1 tAV, TIME IN AVALANCHE (ms) 10
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC 0 1 2 3 4 5 VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
25 2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE -55oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 2.6A 2.0
FIGURE 7. SATURATION CHARACTERISTICS
ID, DRAIN CURRENT (A)
20
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 25oC
150oC
15
1.5
10
5
1.0
0
0
1.5
3.0
4.5
6.0
7.5
0.5 -80
-40
VGS, GATE TO SOURCE VOLTAGE (V)
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A
1.2
VGS = VDS, ID = 250A
NORMALIZED GATE THRESHOLD VOLTAGE
1.0
1.1
0.8
1.0
0.6
0.9
0.4 -80
-40
0
40
80
120
160
0.8 -80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
4
HUF75307T3ST Typical Performance Curves
500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD VGS , GATE TO SOURCE VOLTAGE (V)
(Continued)
10 WAVEFORMS IN DESCENDING ORDER: ID = 2.6A ID = 1.5A ID = 0.5A VDD = 30V
400 C, CAPACITANCE (pF)
8
300 CISS 200 COSS 100 CRSS 0 0 10 20 30 40 50 VDS , DRAIN TO SOURCE VOLTAGE (V) 60
6
4
2
0
0
2
4 Qg, GATE CHARGE (nC)
6
8
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS RL VDD VDS VGS = 20V VGS
+
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Ig(REF) 0 VGS = 10V
DUT Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
5
HUF75307T3ST Test Circuits and Waveforms
VDS
(Continued)
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
DUT RGS
VDD 0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
VGS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJ(MAX), and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PD(MAX), in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJ(MAX) is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
( T J ( MAX ) - T A ) P D ( MAX ) = -------------------------------------------R JA
state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Intersil device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve.
200 RJA = 75.9 -19.3 ln(AREA)
(EQ. 1)
RJA (oC/W) 150 147oC/W - 0.026in2 128oC/W - 0.068in2 110oC/W - 0.171in2 100
In using surface mount devices such as the SOT-223 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of the PD(MAX) is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in.
50 0.01
0.1 AREA, TOP COPPER AREA (in2)
1.0
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
Intersil provides thermal information to assist the designer's preliminary application evaluation. Figure 20 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady
Displayed on the curve are the three RJA values listed in the Electrical Specifications table. The three points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PD(MAX). Thermal resistances corresponding to other component side copper areas can be obtained from Figure 20 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads.
R JA = 75.9 - 19.3 x ln ( Area ) (EQ. 2)
6
HUF75307T3ST PSPICE Electrical Model
.SUBCKT HUF75307T3ST 2 1 3 ;
CA 12 8 3.5e-10 CB 15 14 3.7e-10 CIN 6 8 2.26e-10
10
rev 7/25/97
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
EBREAK 11 7 17 18 57.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.4e-9 LSOURCE 3 7 3.1e-10 K1 LGATE LSOURCE 0.131 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 7.0e-3 RGATE 9 20 1.9 RLDRAIN 2 5 10 RLGATE 1 9 14 RLSOURCE 3 7 3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 5.6e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
GATE 1
ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6
RLGATE CIN
MSTRO LSOURCE 8 RSOURCE RLSOURCE 7 SOURCE 3
S1A 12 S1B CA 13 + EGS 6 8 13 8
S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),3))} .MODEL DBODYMOD D (IS = 2.6e-13 RS = 2.34e-2 IKF = 5.5 N = 0.995 TRS1 = 2.8e-3 TRS2 = 1.1e-5 CJO = 3.7e-10 TT = 3.5e-8 M = 0.46 + XTI = 5.5) .MODEL DBREAKMOD D (RS = 0.5 IKF = 0.1 N = 1 TRS1 = 3e-3 TRS2 = -5e-5) .MODEL DPLCAPMOD D (CJO = 5.6e-10 IS = 1e-30 N = 10 M = 0.92) .MODEL MMEDMOD NMOS (VTO = 3.25 KP = 1.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.9) .MODEL MSTROMOD NMOS (VTO = 3.68 KP = 13.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.83 KP = 0.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 19 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.08e-3 TC2 = 5e-7) .MODEL RDRAINMOD RES (TC1 = 1.7e-2 TC2 = 1e-4) .MODEL RSLCMOD RES (TC1 = 1e-9 TC2 = 1e-4) .MODEL RSOURCEMOD RES (TC1 = 3.3e-3 TC2 = 1e-9) .MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -4e-6) .MODEL RVTEMPMOD RES (TC1 = -2.9e-3 TC2 = 2.2e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -7.1 VOFF= -4) VON = -4 VOFF= -7.1) VON = 0.01 VOFF= 1.9) VON = 1.9 VOFF= 0.01)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
7
+
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
-
RDRAIN 21 16
DBODY
MWEAK MMED
RBREAK 18 RVTEMP 19
VBAT +
8 22 RVTHRES
HUF75307T3ST SPICE Thermal Model
REV 15 Nov 97 HUF75307T3ST CTHERM1 7 6 7.5e-5 CTHERM2 6 5 3.5e-4 CTHERM3 5 4 1.2e-3 CTHERM4 4 3 1.5e-2 CTHERM5 3 2 6.9e-2 CTHERM6 2 1 4.5e-1 RTHERM1 7 6 7.5e-2 RTHERM2 6 5 2.0e-1 RTHERM3 5 4 1.2 RTHERM4 4 3 3.3 RTHERM5 3 2 28 RTHERM6 2 1 90
RTHERM1 CTHERM1 7 JUNCTION
6
RTHERM2
CTHERM2
5
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
1
CASE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
8

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